Dynamic random access memory and boosted voltage producer therefor

ABSTRACT

A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/305,064, filed Nov. 28, 2011, which is a divisional of U.S. patentapplication Ser. No. 11/855,496, filed Sep. 14, 2007, now issued as U.S.Pat. No. 8,072,256, all of which are herein incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to a semiconductor device and inparticular to a boosted voltage producer with charge pump and a dynamicrandom access memory using it.

BACKGROUND OF THE INVENTION

Semiconductor memory devices, such as, for example, dynamic randomaccess memory (DRAM) store data in an array of cells with each cellstoring one bit of data. The cell arrays are typically arranged in rowsand columns such that a particular cell is addressed by specifying itsrow and column within the array. Cells in a row are connected togetherto a wordline and cells in a column are connected together to a bitline.Sense amplifiers connected to the detect data in the cells.

Each of DRAM cells includes a storage capacitor. As such, the cells areconsidered “dynamic”, since the stored data (i.e., charged capacitor)will dissipate after a relatively short period of time. In order toretain the stored data, the contents of the DRAM cells are refreshed ona periodic basis by reapplying the charged state of the storagecapacitor of each cell in a repetitive manner. A refresh operation issimilar to a read operation in that the data in the cells is sensed bythe sense amplifiers and the data is rewritten to the cells. Thus, thedata is “refreshed” in the cells. The refresh operation is performed byenabling a wordline according to a row address and enabling a senseamplifier. Refresh operations can be either “auto-refresh” performedwhen the DRAM is in an active mode or “self-refresh” performed when theDRAM is in a sleep mode.

A boost required for getting from an external supply voltage (Vdd) to agate voltage of access transistor sufficient to charge the capacitors ofthe cells changes with various characteristics of the DRAM. For example,the amount of current boost required overcoming the voltage droppingwhen a refresh operation occurs in the sleep mode increases withdecreasing refresh time. An internal voltage supply is typicallyconfigured without regard to variable refresh times, often relying on aconsideration of only the worst possible refresh times. The refresh rateof the DRAM is typically set by the manufacturer to a time period thatensures that data will not be lost. However, this time period may bemore frequent than necessary and it may be desirable to reduce thisfrequency in order to reduce power consumption. The maximum drivingcapacity of an internal voltage supply is typically determined accordingto the worst refresh characteristics (i.e., the shortest time period).It, thus, provides more current than is required and results in greaterpower consumption.

For example, DRAMs in the 0.13 μm to 0.18 μm size range typically havelonger refresh time periods (e.g., over 8 ms) and as such the sleep modecurrent requirements are low. As the size of DRAMs decreases to around90 nm, MIM (metal-insulator-metal) type capacitors having shorter andmore variable refresh time periods are used. A self-refresh pump circuitmay not easily handle this variability in the voltage boost and currentto be produced. Therefore, the refresh time period may be set accordingto the shortest possible period. If the DRAM has a higher refresh timeperiod, then it may result in over-pumping and inefficient power use inthe sleep mode.

SUMMARY OF THE INVENTION

In accordance with an aspect of the present invention, there is providedan apparatus for producing a boosted voltage, comprising: a plurality ofcharge pump circuitry operative with an input voltage and responsive toa charge pump signal and respective control signals, each of theplurality of charge pump circuitry including a capacitive element. Inthe apparatus, when charge pump circuitry is activated in response to arespective control signal, the capacitive element of the activatedcharge pump circuitry is charged in response to at least one of theinput voltage and the charge pump signal, the charges of the activatedcharge pump circuitry contributing to provide the boosted voltage.

For example, each of the plurality of charge pump circuitry isindividually activatable in response to the respective control signal.By an additional charge pump controller, the control signals may beprovided to the respective charge pump circuitry according toinformation on a charge pump. According to the charge pump controller,charge pump circuitry to be activated is designated.

In accordance with a second aspect of the present invention, there isprovided a method for producing a boosted voltage, comprising: providinga charge pump signal to a plurality of charge pump circuitry, eachincluding a capacitive element; providing respective control signals tothe plurality of charge pump circuitry; and activating charge pumpcircuitry by the respective control signal, so that the capacitiveelement of the activated charge pump circuitry is charged; therebyproducing the boosted voltage with the charges of the activated chargepump circuitry.

For example, the step of activating comprises: activating each of theplurality of charge pump circuitry individually in response to therespective control signal. The step of providing respective controlsignals comprises: providing information for performing the charge pump;and providing the control signal based on the information.

In accordance with another aspect of the present invention, there isprovided a dynamic random access memory (DRAM) having storage cells, thedata of which is refreshed in a sleep mode, the DRAM comprising: avoltage provider for providing an output voltage to be used foroperation of the DRAM; a determiner for determining whether the outputvoltage reaches a predetermined level to provide a determination result;and a controller for providing a control output in response to a refreshtime in the sleep mode, the voltage provider providing a boosted voltageas the output voltage in response to the determination result and thecontrol output.

For example, the voltage provider comprises: boost circuitry forproviding the boosted voltage in response to the control output, theboost circuitry including a plurality of boost operation segments, eachof the boost operation segments being individually activatable inresponse to the control output.

The controller may comprise: a segment selector for providing thecontrol output to select a set of the plurality of boost operationsegments to be activated according to the refresh time, the boostedoutputs from the set of the selected boost operation segments beingcombinable to produce a combined output as the output voltage from thevoltage provider.

In accordance with another aspect of the present invention, there isprovided an apparatus for supplying an operation voltage to a dynamicrandom access memory (DRAM) including storage cells, the data of whichis refreshed in a sleep mode of the DRAM, the apparatus comprising:first and second voltage suppliers for supplying a word bootstrappingvoltage and a substrate bias voltage for use in the DRAM, the wordbootstrapping voltage and the substrate bias voltage being varied inresponse to a refresh time in the sleep mode.

For example, the first voltage supplier comprises: a first voltageprovider for providing a first output voltage to be used for operationof the DRAM; and a first determiner for determining whether the firstoutput voltage reaches a first predetermined level to provide a firstdetermination result.

The second voltage supplier may comprise: a second voltage provider forproviding a second output voltage to be used for operation of the DRAM;and a second determiner for determining whether the second outputvoltage reaches a second predetermined level to provide a seconddetermination result.

In accordance with another aspect of the present invention, there isprovided a method for producing a boosted voltage for a dynamic randomaccess memory (DRAM) having storage cells, the data of which isrefreshed in a sleep mode, the method comprising: providing an outputvoltage to be used for operation of the DRAM; determining whether theoutput voltage reaches a predetermined level to provide a determinationresult; and providing a control output in response to a refresh time inthe sleep mode, thereby providing a boosted voltage as the outputvoltage in response to the determination result and the control output.

In accordance with another aspect of the present invention, there isprovided a method for supplying an operation voltage to a dynamic randomaccess memory (DRAM) including storage cells, the data of which isrefreshed in a sleep mode of the RAM, the method comprising: supplying aword bootstrapping voltage; and supplying a substrate bias voltage foruse in the DRAM, the word bootstrapping voltage and the substrate biasvoltage being varied in response to a refresh time in the sleep mode.

For example, the step of supplying a word bootstrapping voltagecomprises: providing an output voltage to be used for operation of theDRAM; determining whether the output voltage reaches a predeterminedlevel to provide a determination result; and providing a control outputin response to a refresh time in the sleep mode, thereby providing aboosted voltage as the output voltage in response to the determinationresult and the control output.

The step of supplying a substrate bias voltage may comprise: providingan output voltage, the output voltage being used for operation of theDRAM; determining whether the output voltage reaches a predeterminedlevel to provide a determination result; and providing a control outputin response to a refresh time in the sleep mode, thereby providing aboosted voltage as the output voltage in response to the determinationresult and the control output.

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 is a block diagram illustrating a configuration of producing aboosted voltage according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a dynamic random access memory(DRAM) according to another embodiment of the present invention;

FIG. 3 is a block diagram illustrating details of an example of a wordbootstrapping voltage generator shown in FIG. 2;

FIG. 4 is a block diagram illustrating an example of a pump signalprovider shown in FIG. 3;

FIG. 5 is a block diagram illustrating an example of a pump segmentenable controller shown in FIG. 3;

FIG. 6 illustrates an example of a segment of a sleep mode pump circuitshown for the word bootstrapping voltage generator in FIG. 3;

FIG. 7 is a flow chart of operations performed by the word bootstrappingvoltage generator shown in FIG. 3;

FIG. 8 is a block diagram illustrating another example of a pump signalprovider shown in FIG. 3;

FIG. 9 is a flow chart of operations performed by the word bootstrappingvoltage generator having the pump signal provider shown in FIG. 8;

FIG. 10 is a block diagram illustrating another example of a pump signalprovider shown in FIG. 3;

FIG. 11 is a block diagram illustrating details of an example of asubstrate bias voltage generator shown in FIG. 2;

FIG. 12 is a block diagram illustrating an example of a pump signalprovider shown in FIG. 11;

FIG. 13 illustrates an example of a segment of a sleep mode pump circuitfor the substrate bias voltage generator shown in FIG. 12;

FIG. 14 is a flow chart of operations performed by the substrate biasvoltage generator shown in FIG. 11;

FIG. 15 is a block diagram illustrating another example of a pump signalprovider shown in FIG. 11;

FIG. 16 is a flow chart of operations performed by the substrate voltagegenerator having the pump signal provider shown in FIG. 15;

FIG. 17 is a block diagram illustrating another example of a pump signalprovider shown in FIG. 11;

FIG. 18 is a block diagram illustrating another example of a dynamicrandom access memory (DRAM) according to another embodiment of thepresent invention;

FIG. 19 is a block diagram illustrating details of an example of a wordbootstrapping voltage generator shown in FIG. 18; and

FIG. 20 is a block diagram illustrating an example of a substrate biasvoltage generator shown in FIG. 18.

DETAILED DESCRIPTION

In the following detailed description of sample embodiments, referenceis made to the accompanying drawings, which form a part hereof and inwhich is shown by way of illustration specific sample embodiments. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the present invention and it is to be understoodthat other embodiments may be used and that logical, mechanical,electrical and other changes may be made without departing from thescope of the present invention. Therefore, the following detaileddescription is not to be taken in a limiting sense.

Generally, the present invention provides a boosted voltage producerwith charge pump circuitry.

FIG. 1 shows a configuration of producing a boosted voltage according toan embodiment of the present invention. Referring to FIG. 1, a boostedvoltage producer includes a group of charge pump circuitry CP_1, CP_2, .. . , CP_m-1 and CP_m, m being an integer greater than one. Each of thecharge pump circuitry CP_1, CP_2, . . . , CP_m-1 and CP_m includes acapacitive element CPE therein and receives an input voltage Vi. Also,the boosted voltage producer includes an activation controller CPC for acharge pump. The activation controller CPC provides a group of chargepump activation signals CPA_1, CPA_2, . . . , CPA_m-1 and CPA_m tocharge pump circuitry CP_1, CP_2, . . . , CP_m-1 and CP_m, respectively,in response to an input signal IN containing information on charge pump.Each of the charge pump circuitry CP_1, CP_2, . . . , CP_m-1 and CP_mreceives a pump signal CPS that is a repetition signal having two levelsof “high” and “low”, such as an oscillation signal provided from anoscillator (not shown).

In response to the respective one of the charge pump activation signalsCPA_1, CPA_2, . . . , CPA_m-1 and CPA_m, the charge pump circuitry isactivated. The activated charge pump circuitry performs the voltageboost function and current pumping, in response to the pump signal CPS.

The boosted voltage producer provides a boosted output voltage Vo to aload LD, such as, for example, a semiconductor device and memorycircuitry, which has a capacitive element LCP. The boosted voltage maybe positive or negative. In the cases of producing a positive voltageVop and a negative voltage Von, the input voltage Vi is a positivevoltage Vip and a zero voltage Vio, respectively.

In the producer of a positive boosted voltage Vop, the capacitiveelement CPE in each of the activated charge pump circuitry is charged bythe input voltage Vip in response to the pump signal CPS having a onelevel (e.g., “low”). When the pump signal CPS is in the other level(e.g., “high”), the charged voltage level at each of the activatedcharge pump circuitry is boosted and the charge of the capacitiveelement CPE is shared with the capacitive element LCP of the load LD.Therefore, current flows from the activated charge pump circuitry to theload LD. As a result, combined charges of all capacitive elements CPE inthe activated charge pump circuitry contribute a production of thepositive boosted output voltage Vop and current pumping from the chargepump circuitry CP_1, CP_2, . . . , CP_m-1 and CP_m.

In the producer of a negative boosted voltage Von, in response to thepump signal CPS having a one level (e.g., “high”), the capacitiveelement CPE in each of the activated charge pump circuitry is charged bythe “high” level voltage. When the pump signal CPS is in the other level(e.g., “low”), the charge of the capacitive element CPE is shared withthe capacitive element LCP of the load LD. As a result, combined chargesof all capacitive elements CPE in the activated charge pump circuitrycontribute a production of the negative boosted output voltage Von andcurrent pumping from the charge pump circuitry CP_1, CP_2, . . . ,CP_m-1 and CP_m.

With the information contained in the input signal IN, the charge pumpactivation controller CPC determines which charge pump circuitry areactivated. In the case where each of the charge pump circuitry CP_1,CP_2, . . . , CP_m-1 and CP_m is capable of providing the same amount ofcharge, the combined charge is proportional to the number of theactivated charge pump circuitry.

Such a boosted voltage producer as shown in FIG. 1 is applicable tosemiconductor devices, such as, for example, random access memories(DRAMs). Examples of DRAMs to which boosted voltage producers areapplied will be described.

FIG. 2 shows an example of a dynamic random access memory (DRAM)according to another embodiment of the present invention. Referring toFIG. 2, a DRAM 100 stores data in an array of cells with each cellstoring one bit. The DRAM 100 includes a memory array 102 that is anarray of cells in which cells in a row are connected together by awordline and in a column by a bitline. The wordlines and bitlines areused to access a specific cell. Each of the cells includes, for example,a storage capacitor (not shown) for storing data. The cells areconsidered to be “dynamic” since the stored data (i.e., charge of acapacitor) will dissipate after a relatively short period of time. Inorder to retain the stored data, the contents of the DRAM cells arerefreshed on a periodic basis by reapplying the charged state to thestorage capacitors. The maximum allowable time between refreshoperations is determined by charge storage capabilities of the storagecapacitors. A refresh time is typically set to guarantee data retentionin the cells.

A refresh operation is similar to a read operation but without anyoutput of data. The data in the cells is sensed by the sense amplifiersbefore a refresh operation that results in data being rewritten to thecells to refresh the data. The refresh operation is performed byenabling a wordline according to a row address and enabling a senseamplifier. Refresh operations can be either “auto-refresh” or“self-refresh.” With an auto-refresh operation a refresh command isperiodically generated during operation of the DRAM 100 and all othercommands are interrupted while the refresh is performed. A self-refreshoperation is performed on a periodic basis when the DRAM 100 is in asleep mode to prevent data loss.

The DRAM 100 includes a row decoder 104 for driving the wordlines andsense amplifiers and bitline access circuits 106 for transferring datainto and out of the cells via the bitlines. Data path circuits include adata I/O circuit 114 that couples data between the sense amplifiers andbitline access circuits 106 and data input/output buffers 116.Addressing circuits include a row address predecoder 108 for generatinga predecoded row address in response to a row address signal 130 and acolumn address decoder 110 for activating bitline access devices inresponse to a column address signal 132. The sense amplifiers andbitline access circuits 106 store and restore data in the cells of thememory array 102 by charging the capacitors of the cells.

In the particular example shown in FIG. 2, an internal voltage supply112 generates voltages for operation of the DRAM 100 based on receipt ofan external supply voltage Vdd and operates in response to an operationmode signal 128 and the sleep mode pump control signal 122. The sleepmode pump control signal 122 includes a word bootstrapping controlsignal 124 and a substrate bias control signal 126. Each of the wordbootstrapping control signal 124 and the substrate bias control signal126 provide an indication of the refresh time of the DRAM 100. Theoperation mode signal 128 provides an indication of whether the DRAM 100is in the sleep mode or active mode. The internal voltage supply 112includes a word bootstrapping voltage generator 118 and a substrate biasvoltage generator 120 to which the word bootstrapping control signal 124and the substrate bias control signal 126 are directed, respectively.

The word bootstrapping voltage generator 118 generates a positive wordbootstrapping voltage Vpp in response to the operation mode of the DRAM100 (e.g., the self-refresh/sleep mode or auto/active mode) as indicatedin the operation mode signal 128. The word bootstrapping voltage Vpp isprovided to memory circuitry, e.g., the row decoder 104. The wordbootstrapping voltage Vpp can be used for driving wordlines of the DRAM100. The word bootstrapping voltage generator 118 is a charge pump-basedcircuit and can have both an active voltage circuit for auto-refreshmode and normal read/write operations and a sleep mode pump circuit forself-refresh mode.

The substrate bias voltage generator 120 provides a negative substratebias voltage Vbb that is provided to the memory circuitry, e.g., thecells of the memory array 102 to ensure stable cell-array operation. Aswith the word bootstrapping voltage generator 118, the substrate biasvoltage generator 120 has also a charge pump circuit. The wordbootstrapping voltage generator 118 and the substrate bias voltagegenerator 120 can be active at the same time in response to theoperation mode signal 128. The word bootstrapping voltage generator 118and the substrate bias voltage generator 120 perform boost operations inresponse to the word bootstrapping control signal 124 and the substratebias control signal 126, respectively.

The boost required getting from Vdd to the word bootstrapping voltageVpp or the substrate bias voltage Vbb changes with variouscharacteristics of the DRAM 100. The refresh rate of the DRAM 100 istypically set to a time period that ensures that data will not be lost.However, this time period can be more frequent than necessary and it isdesirable to reduce this frequency in order to reduce power consumption.With a shorter refresh time period, there is an increase in the internalpower consumption of the DRAM 100, requiring more current as a result.In general, pump circuits are typically configured according to theworst refresh characteristics (i.e., the shortest time period) and thusprovides more current than is required, resulting in greater powerconsumption. Temperature monitoring and variable refresh rate controlcircuits can change the refresh rate, if provided.

FIG. 3 shows an example of the word bootstrapping voltage generator 118shown in FIG. 2. Referring to FIGS. 2 and 3, the word bootstrappingvoltage generator 118 includes an active voltage circuit 202 and avoltage level detector 212. When the DRAM 100 is in the active mode andthe sleep mode, the operation mode signal 128 is “high” and “low”,respectively. In response to the “high” and “low” operation mode signal128, the active voltage circuit 202 is activated and deactivates,respectively. In the active mode, the active voltage circuit 202 isactivated and the word bootstrapping voltage Vpp is produced. If theword bootstrapping voltage Vpp is lower than a predetermined voltagelevel, the voltage level detector 212 will output a level detectionsignal 220 of logic “high”. In response to the “high” level detectionsignal 220, the active voltage circuit 202 performs boost operation.

The word bootstrapping voltage generator 118 also performs boostoperation when the DRAM 100 is in the sleep mode. Such a sleep modeboost operation is performed by similar circuitry as the active voltagecircuit 202. The sleep mode boost operation circuitry includes a pumpsignal provider 200 and a sleep mode pump circuit 208. In the particularexample shown in FIG. 3, the sleep mode pump circuit 208 has a pluralityof pump segments. The sleep mode boost operation circuitry furtherincludes a pump segment enable controller 206 for selectively activatingthe segments of the sleep mode pump circuit 208. The word bootstrappingvoltage generator 118 receives information regarding the refresh timeperiod that is being used for the DRAM 100 and uses this information toproduce the word bootstrapping voltage Vpp according to the refresh timeperiod when the DRAM 100 is in the sleep mode,

The voltage level detector 212 determines the voltage level of the wordbootstrapping voltage Vpp to provide a determination result. The voltagelevel detector 212 monitors the word bootstrapping voltage Vpp andproduces the level detection signal 220 to indicate whether or not theword bootstrapping voltage Vpp is higher or lower a positivepredetermined voltage Vdtp. The level detection signal 220 is used bythe active voltage circuit 202 and the pump signal provider 200 eitherdirectly or indirectly to adjust the voltage output such that the wordbootstrapping voltage Vpp remains approximately constant, regardless ofwhether or not the DRAM 100 is in the sleep mode or active mode.

FIG. 4 shows an example of the pump signal provider 200 shown in FIG. 3.Referring to FIGS. 3 and 4, the operation mode signal 128 is inverted byan inverter 224 and its inverted output signal and the level detectionsignal 220 are fed to an AND gate 232. An output oscillation activationsignal 230 from the AND gate 232 is fed to a sleep mode oscillator 210which in turn provides a sleep mode oscillation signal 234 to the sleepmode pump circuit 208.

The level detection signal 220 is provided to the active voltage circuit202 and the pump signal provider 200. When the word bootstrappingvoltage Vpp is lower than a predetermined level Vdtp of the voltagelevel detector 212, the “high” level detection signal 220 is provided.With the “high” level detection signal 220, the active voltage circuit202 or the pump signal provider 200 is activated in response to theoperation mode signal 128. The voltage level detector 212 is in afeedback loop with both the active voltage circuit 202 and the sleepmode pump circuit 208 to achieve a constant voltage for the wordbootstrapping voltage Vpp. When the word bootstrapping voltage Vpp ishigher than the predetermined level Vdtp, the “low” level detectionsignal 220 is provided. The voltage level detector 212 is in a feedbackloop with both the active pump circuit 202 and the sleep mode pumpcircuit 208 to maintain a constant voltage for the word bootstrappingvoltage Vpp.

When the DRAM 100 enters the sleep mode, the operation mode signal 128indicates that the DRAM 100 is in the sleep mode and the boost operationis to be performed if necessary. The boost operation for theself-refresh is performed by the sleep mode oscillator 210, the pumpsegment enable controller 206, the sleep mode pump circuit 208 and thevoltage level detector 212.

The operation mode signal 128 is provided to the inverter 224 and itsinverted output logic signal is combined with the level detection signal220 by the AND gate 232 to activate the sleep mode oscillator 210. Inthe case of the sleep mode, in response to the level detection signal220, the AND gate 232 provides the “high” oscillation activation signal230 to the sleep mode oscillator 210 for the generation of the sleepmode oscillation signal 234.

The sleep mode pump circuit 208 pumps only at the edges of the sleepmode oscillation signal 234. Since the current requirements of the DRAM100 in the sleep mode is lower than in the active mode, the frequency ofthe sleep mode oscillation signal 234 can be lower than the frequency ofan oscillation signal of the active voltage circuit 202.

The sleep mode pump circuit 208 receives the sleep mode oscillationsignal 234 from the sleep mode oscillator 210 and a pump enable signal238 from the pump segment enable controller 206. The pump enable signal238 indicates the amount of charge pump or current driven by the sleepmode pump circuit 208.

The pump segment enable controller 206 receives the word bootstrappingcontrol signal 124 including a group of refresh time signals 124_1,124_2, . . . , 124 _(—) n-1 and 124 _(—) n, where n is an integergreater than one. The word bootstrapping control signal 124 containsinformation on the refresh time period for the DRAM 100. The refreshtime period can be a preset time provided by the manufacturer or a timeset by a user. Further, this refresh time can be static (e.g., the samevalue regardless of the operating conditions of the DRAM) or dynamic toadapt to changing operating conditions (e.g., temperature, etc.). Eachof the refresh time signals 124_1, 124_2, . . . , 124 _(—) n-1 and 124_(—) n represents a possible refresh time period. When the refresh timesignal 124_1, 124_2, . . . , 124 _(—) n-1 or 124 _(—) n is “high”, itindicates the refresh time used by the DRAM 100. The pump segment enablecontroller 206 uses this indication of the refresh time to determine howmuch voltage boost and current pumping the sleep mode pump circuit 208provide. Since voltage and current requirements in the DRAM 100 will begreater with shorter refresh times, the shorter refresh times willresult in greater current pumping. In response to the pump enable signal238 from the pump segment enable controller 206, the sleep mode pumpcircuit 208 performs the voltage boost and current pumping. Table 1shows examples of the refresh times Ref_1 p, Ref_2 p, . . . , Ref_n-1 pand Ref_np represented by the refresh time signal 124_1, 124_2, . . . ,124 _(—) n-1 and 124 _(—) n, respectively.

TABLE 1 Refresh Time Ref_1p Ref_2p . . . Ref_n-1p Ref_np 1 ms 2 ms . . .(n-1) ms n ms (1 ms) × 1 (1 ms) × 2 (1 ms) × (n-1) (1 ms) × n

The sleep mode pump circuit 208 includes a plurality of pump circuitsegments 240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—) z, z being aninteger greater than one. Each of the pump circuit segments 240_1,240_2, . . . , 240 _(—) z-1 and 240 _(—) z provides a small,predetermined amount of voltage boost and current pumping. The pumpsegment enable controller 206 determines which of the pump circuitsegments 240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—) z are to beactivated to perform the boost operation.

The group of pump segment enable signals 238_1, 238_2, . . . , 238 _(—)z-1 and 238 _(—) z are sent to the respective pump circuit segments240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—) z. When the pump segmentenable signals 238_1, 238_2, . . . , 238 _(—) z-1 and 238_(—) z arehigh, the pump circuit segments 240_1, 240_2, . . . , 240 _(—) z-1 and240 _(—) z receiving the high signals are activated. In the particularexample shown in FIGS. 3 and 4, the voltage boost performed by each ofthe pump circuit segment 240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—)z is the same for every segment. The amount of voltage boost is limitedby the voltage level detector 212. When the voltage boost is excessive(Vpp>Vdtp), the voltage level detector 212 outputs the “low” leveldetection signal 220 effectively stops the sleep mode pump circuit 208from continuing to boost the voltage.

The current output by or flowing in each of the pump circuit segments240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—) z has an additiveeffect. The activated pump circuit segments 240_1, 240_2, . . . , 240_(—) z-1 and 240 _(—) z increase the current output by the sleep modepump circuit 208. Since a greater amount of current is used when theDRAM 100 has faster refresh times, the pump segment enable controller206 activates a greater number of the pump circuit segments 240_1,240_2, . . . , 240 _(—) z-1 and 240 _(—) z.

FIG. 5 shows an example of the pump segment enable controller 206 shownin FIG. 3. Referring to FIG. 5, the pump segment enable controller 206includes a plurality (n) of OR logic circuits 304_1, 304_2, . . . , 304_(—) n-1 and 304 _(—) n, n being an integer greater than one. Each ofthe OR logic circuits 304_1, 304_2, . . . , 304 _(—) n-1 and 304 _(—) nis formed by a series-connected NOR gate 300 and inverter 302.

The refresh time signals 124_1, 124_2, . . . , 124 _(—) n-1 and 124 _(—)n represent the refresh time of the DRAM 100. At a time only one of therefresh time signals 124_1, 124_2, . . . , 124 _(—) n-1 and 124 _(—) nis “high” and the others are “low”. Each of the refresh time signals124_1, 124_2, . . . , 124 _(—) n-1 and 124 _(—) n is provided as oneinput of the respective NOR gate 300. The other input of the NOR gate300 in each of the OR logic circuits 304_2, . . . , 304 _(—) n-1 and 304_(—) n is an output from the previous OR logic circuit 304_1, 304_2, . .. , and 304 _(—) n-1. The other input of the NOR gate 300 of the ORlogic circuit 304_1 is pulled down (i.e., logic “low”).

The outputs of the OR logic circuits 304_1, 304_2, . . . , 304 _(—) n-1and 304 _(—) n produce the pump segment enable signals 238 _(—) z, 238_(—) z-1, . . . , 238_2 and 238_1, respectively. Since the output of oneof the OR logic circuits 304_1, 304_2, . . . , 304 _(—) n-2 and 304 _(—)n-1 is provided as an input of the next OR logic circuit 304_2, . . . ,304 _(—) n-1 and 304 _(—) n, if the shortest refresh time signal (inthis case Ref_1 p (=1 ms) represented by the signal 124_1) is high, allof the pump segment enable signals 238_1, 238_2, . . . , 238 _(—) z-1and 238 _(—) z will be high, so that all of the pump circuit segments240_1, 240_2, . . . , 240 _(—) z-1 and 240 _(—) z will be turned on toprovide maximum current pumping. If the second shortest refresh timesignal (in this case Ref_2 p (=2 ms) represented by the signal 124_2) ishigh, every segment other than one is turned on. If the longest refreshtime signal (in this case Ref_np (=n ms) represented by the signal 124_(—) n) is high then only the first segment is turned on. Table 2 showsan example of how the pump circuit segments 240_1, 240_2, . . . , 240_(—) z-1 and 240 _(—) z are activated according to the refresh time.

TABLE 2 Refresh Time and Segment Activation Refresh Time Segment 1Segment 2 Segment Z-1 Segment Z (ms) 240_1 240_2 . . . 240_z-1 240_z 1ACT ACT . . . ACT ACT 2 ACT ACT . . . ACT NO-ACT . . . . . . . . . . . .. . . . . . n − 1 ACT ACT . . . NO-ACT NO-ACT n ACT NO-ACT . . . NO-ACTNO-ACT

In Table 2, “ACT” and “NO-ACT” represent “activated” and“non-activated”, respectively.

FIG. 6 shows an example of one segment of the sleep mode pump circuit208 shown in FIG. 3. Referring to FIG. 6, a segment 240 _(—) irepresents any one of the pump circuit segments 240_1, 240_2, . . . ,240 _(—) z-1 and 240 _(—) z. The pump circuit segment 240 _(—) iincludes an AND logic circuit 404, a capacitor 406, a drain-gateconnected clamp transistor 408 and a drain-gate connected drivetransistor 412. The AND logic circuit 404 is formed by an NAND gate 400and an inverter 402 connected thereto. The output of the AND logiccircuit 404 is connected through the capacitor 406 to the clamptransistor 408 and the drive transistor 412. The NAND gate 400 receivesthe sleep mode oscillation signal 234 and the pump segment enable signal238 _(—) i. The pump segment enable signal 238 _(—) i is a signal fromthe pump segment enable controller 206.

The capacitor 406 corresponds to the capacitive element CPE of FIG. 1.The memory circuitry receiving the word bootstrapping voltage Vpp has acapacitive element Cpp, which corresponds to the capacitive element LCPshown in FIG. 1. Such a capacitive element Cpp, therefore, shares thecharge of the capacitor 406 and current can flow from the capacitor 406to the memory circuitry.

Referring to FIGS. 2-6, in the particular example shown therein, each ofthe pump circuit segments 240_1, 240_2, . . . , 240 _(—) z-1 and 240_(—) z produces the same amount of voltage boost and current pumping, inresponse to the sleep mode oscillation signal 234. When the DRAM 100 isin the sleep mode (i.e., the operation mode signal 128 is high) and theword bootstrapping voltage Vpp is to be boosted (i.e., the leveldetection signal 220 is high), in response to the sleep mode oscillationsignal 234, the pump circuit segment 240 _(—) i performs the pumpfunction and the boosted word bootstrapping voltage Vpp is provided.During the sleep mode oscillation signal 234 is low, the capacitor 406is charged by Vdd-Vthn through the clamp transistor 408 and then, duringthe sleep mode oscillation signal 234 is high, the charge voltage at apoint, referenced by 410, is boosted by the voltage of the sleep modeoscillation signal 234. Vthn is an NMOS threshold voltage.

The drive transistor 412 is a one-direction driver that is open whilethe voltage at point 410 is positive. The drive transistor 412 is off,when the voltage at point 410 is falling. With the boost functionperformed by the segment 240 _(—) i, the word bootstrapping voltage Vppslowly increases. The result is that the charges of all activated pumpcircuit segments are combined to produce the word bootstrapping voltageVpp to achieve an increased boosted current.

In a configuration of the segment 240 shown in FIG. 6, every segment isthe same, producing the same voltage and current. A person of skill inthe art will understand that the segments can be configured to producedifferent currents.

FIG. 7 shows the operation of the word bootstrapping voltage generatorof FIG. 3. Referring to FIGS. 2-6, the DRAM 100 operates (step 502) andthe DRAM operation mode is determined whether it is the sleep mode (step504) according to the operation mode signal 128. In the case of the“high” operation mode signal 128, the DRAM operation mode is the activemode (NO at step 504). Then, the active voltage circuit 202 is activatedto generate the word bootstrapping voltage Vpp for the active modeoperation (step 506).

In the “low” operation mode signal 128, the DRAM operation mode is thesleep mode (YES at step 504). Thereafter, the word bootstrapping voltageVpp is compared to the predetermined level Vdtp to determine the formeris lower than the latter (step 508). In the case where the wordbootstrapping voltage Vpp is higher than the determined level Vdtp, thevoltage level detector 212 provides the “low” level detection signal 220(NO at step 508). Then, the DRAM operation is performed (step 502).

In the case where the word bootstrapping voltage Vpp is lower than thedetermined level Vdtp, the voltage level detector 212 provides the“high” level detection signal 220 (YES at step 508). The “high” leveldetection signal 220 and the “low” operation mode signal 128 result inthe “high” oscillation activation signal 230 and the sleep modeoscillator 210 generates the sleep mode oscillation signal 234 (step510). Then, the sleep mode oscillation signal 234 is provided to thesleep mode pump circuit 208 (step 512).

Segments of the sleep mode pump circuit 208 are selected for activationbased on a refresh rate (step 514). In other words, if the refresh rateindicates frequent refresh operations then a greater number of segmentswill be activated due to the larger current used in the DRAM 100. Basedon the selected segments, pump segment activation signals are generated(step 516). In response to the generated pump segment activationsignals, the pump circuit segments are selected and the selectedsegments are activated (step 518).

The outputs from the selected segments are combined to produce the wordbootstrapping voltage Vpp (step 520). The DRAM 100 is operated with theword bootstrapping voltage Vpp (step 502). In the sleep mode, theoperations of steps 508-520 are repeated. If the word bootstrappingvoltage Vpp becomes higher than the predetermined level Vdtp (NO at step508), the voltage boost and current pumping are ceased.

FIG. 8 shows another example of the pump signal provider 200 shown inFIG. 3. The pump signal provider 200 shown in FIG. 8 is similar to thatof FIG. 4. In the example illustrated in FIG. 8, the sleep modeoscillator 210 is activated by the operation mode signal 128 and anoutput oscillation signal 330 of the sleep mode oscillator 210 is fed tothe AND gate 232. Operations performed by the DRAM implementing the pumpsignal provider of FIG. 8 are shown in FIG. 9. The operations shown inFIG. 9 are similar to those of FIG. 7. The operations conducted in steps508 and 510 are reversed. In the operations of FIG. 9, when the DRAMoperation mode is determined as the sleep mode (YES at step 504), thensleep mode oscillator 210 generates the oscillation signal 330 (step510) and the, it is determined whether the word bootstrapping voltageVpp is lower than the determined level Vdtp (step 508). Therefore, theoscillation signal is always produced, but only provided to the pumpcircuit, when the level detection signal 220 is high.

FIG. 10 shows another example of a pump signal provider shown in FIG. 3.In the example illustrated in FIG. 10, an oscillator 310 is activated bya power up signal and its oscillation output signal 340 is provided tothe AND gate 232. The operation performed by the pump signal provider ofFIG. 10 is similar to that of FIG. 8.

FIG. 11 shows an example of the substrate bias voltage generator 120shown in FIG. 2. The configuration of the substrate bias voltagegenerator 120 is similar to that of the word bootstrapping voltagegenerator 118. The substrate bias voltage generator 120 functions in thesame manner as that of the word bootstrapping voltage generator 118 toproduce such a boosted voltage as the substrate bias voltage Vbb. Thesubstrate bias voltage Vbb is a negative voltage.

Referring to FIGS. 2 and 11, similarly to the word bootstrapping voltagegenerator 118, the substrate bias voltage generator 120 includes anactive voltage circuit 714 and a voltage level detector 718. In thisparticular example, the voltage level detector 718 determines whetherthe substrate bias voltage Vbb is higher or lower than a negativepredetermined voltage Vdtn and outputs a level detection signal 716 as adetermination result. In response to the “high” and “low” operation modesignal 128 in the active and sleep mode of the DRAM 100, the activevoltage circuit 714 is activated and deactivated, respectively.

The substrate bias voltage generator 120 performs a sleep mode boostoperation by a pump signal provider 700, a sleep mode pump circuit 712and a pump segment enable controller 720. The sleep mode pump circuit712 has a plurality of pump segments 710_1, 710_2, . . . , 710 _(—) z-1and 710 _(—) z that are selectively activated by the pump segment enablecontroller 720, where z is an integer greater than one. The substratebias voltage generator 120 receives information regarding the refreshtime period in the sleep mode and produces the substrate bias voltageVbb according to the refresh time period. The configuration andoperation of the pump segment enable controller 720 are the same asthose of the pump segment enable controller 206 of FIGS. 3 and 5.

The voltage level detector 718 monitors the substrate bias voltage Vbbto produce the level detection signal 716. Since the substrate biasvoltage Vbb is negative, the level detection signal 716 is “high” and“low” when the substrate bias voltage Vbb is higher and lower than thepredetermined level Vdtn, respectively.

The pump signal provider 700 has the same circuitry as shown in FIG. 4.The pump signal provider 700 provides a sleep mode oscillation signal706 to the sleep mode pump circuit 712 when the operation mode signal128 is “low” and the level detection signal 716 is “high”. The sleepmode oscillation signal 706 corresponds to the sleep mode oscillationsignal 234 of FIG. 4.

FIG. 12 shows an example of the pump signal provider 700 shown in FIG.11. The particular example shown in FIG. 12 has the same circuit as thatof FIG. 4.

Referring to FIGS. 2, 11 and 12, the AND gate 232 receives the leveldetection signal 716 and an inverted signal of the operation mode signal128 to activate the sleep mode oscillator 210 that provide the sleepmode oscillation signal to the sleep mode pump circuit 712. The pumpsegment enable controller 720 receives the substrate bias control signal126 including refresh time signals 126_1, 126_2, . . . , 126 _(—) n-1and 126 _(—) n that represent possible refresh times for the DRAM, Ref_1b, Ref_2 b, . . . , Ref_n-1 b and Ref_nb. The refresh times Ref_1 b,Ref_2 b, . . . , Ref_n-1 b and Ref_nb can be different from or the sameas the Ref_1 p, Ref_2 p, . . . , Ref_n-1 p and Ref_np for the wordbootstrapping voltage generator 118. The pump segment enable controller720 uses this indication of the refresh time. The pump segment enablecontroller 720 provides a pump enable signal 722 including a pluralityof pump segment enable signals 722_1, 722_2, . . . , 722 _(—) z-1 and722 _(—) z to activate the sleep mode pump circuit 712.

The sleep mode pump circuit 712 receives the sleep mode oscillationsignal 706 from the pump signal provider 700 as well as the pump segmentenable signals 722_1, 722_2, . . . , 722 _(—) z-1 and 722 _(—) z. Thepump segment enable controller 720 determines which of these segments710_1, 710_2, . . . , 710 _(—) z-1 and 710 _(—) z are to be activated toprovide the amount of voltage boost and current pumping for self-refreshoperation. The segments 710_1, 710_2, . . . , 710 _(—) z-1 and 710 _(—)z are activated on the basis of the pump segment enable signals 722_1,722_2, . . . , 722 _(—) z-1 and 722 _(—) z.

When the substrate bias voltage Vbb goes lower than the negativepredetermined level Vdtn, the “low” level detection signal 716 isprovided to stop the sleep mode pump circuit 712 from continuing toboost the voltage. When the substrate bias voltage Vbb goes higher thanthe negative predetermined level Vdtn, the “high” level detection signal716 is provided to perform the voltage boost operation. The currentpumped by each of the segments 710_1, 710_2, . . . , 710 z-1 and 710_(—) z has an additive effect, so that the segments 710_1, 710_2, . . ., 710 _(—) z-1 and 710 _(—) z can be activated to increase the currentpumped by the sleep mode pump circuit 712.

FIG. 13 shows an example of a segment of the sleep mode pump circuit 712shown in FIG. 11. Referring to FIG. 13, a pump circuit segment 710 _(—)i represents any one of the pump circuit segments 710_1, 710_2, . . . ,710 _(—) z-1 and 710 _(—) z shown in FIG. 11. The pump circuit segment710 _(—) i includes an AND logic circuit 740, a capacitor 734, adrain-gate connected clamp transistor 738 and a drain-gate connecteddrive transistor 736. The AND logic circuit 740 is formed by a NAND gate730 and an inverter 732 connected thereto. The pump circuit segment 710_(—) i has a configuration similar to the segment 240 _(—) i for theword bootstrapping voltage generator 118 shown in FIG. 2. The clamptransistor 738 is connected to the ground. The drive transistor 736 isreversely biased due to the negative voltage produced by the segment 710_(—) i. The output of the AND logic circuit 740 is connected through thecapacitor 734 to the clamp transistor 738 and the drive transistor 736.The NAND gate 740 receives the sleep mode oscillation signal 706 and thepump segment enable signal 722 _(—) i from the pump segment enablecontroller 720.

Referring to FIGS. 11 and 13, when the DRAM 100 is in the sleep mode and“high” pump segment enable signal 722 _(—) i, during the sleep modeoscillation signal 706 is high, the capacitor 734 is charged through theclamp transistor 738. Then, during the sleep mode oscillation signal 706is low, the charge voltage at a point, referenced by 744, is boosted.Thus, the substrate bias voltage Vbb is provided to the memorycircuitry, which has a capacitive element Cbb. The capacitive elementCbb corresponds to the capacitive element LCP shown in FIG. 1 and sharesthe charge with the capacitor 734 through the drive transistor 736.Therefore, the charges of all activated pump circuit segments arecombined to produce the negative substrate bias voltage Vbb

The pump circuit segment 710 _(—) i shown in FIG. 13 illustrates aconfiguration in which every segment is the same, producing the samevoltage and current. A person of skill in the art will understand thatthe segments can be configured that only a single segment is activatedor multiple segments is activated.

FIG. 14 shows operations of the substrate bias voltage generator of FIG.11. Referring to FIGS. 2 and 11-14, the DRAM 100 operates (step 802) andthe DRAM operation mode is determined whether it is the sleep mode (step804) according to the operation mode signal 128. In the case of the“high” operation mode signal 128, the DRAM operation mode is the activemode (NO at step 804). Then, the active voltage circuit 714 is activatedto generate the word bootstrapping voltage Vbb for the active modeoperation (step 806).

In the “low” operation mode signal 128, the DRAM operation mode is thesleep mode (YES at step 804). Thereafter, the substrate bias voltage Vbbis compared to the negative predetermined level Vdtn to determine theformer is higher than the latter (step 808). In the case where thesubstrate bias voltage Vbb is lower than the determined level Vdtn, thevoltage level detector 718 provides the “low” level detection signal 716(NO at step 808). Then, the DRAM operation is performed (step 802).

In the case where the substrate bias voltage Vbb is higher than thedetermined level Vdtn, the voltage level detector 718 provides the“high” level detection signal 716 (YES step 808). The “high” leveldetection signal 716 and the “low” operation mode signal 128 result inthe “high” oscillation activation signal 230 and the sleep modeoscillator 210 generates the sleep mode oscillation signal 706 (step810). The sleep mode oscillation signal 706 is provided to the sleepmode pump circuit 712 (step 812). Based on a refresh rate, the pumpsegment activation signals are generated (step 816). In response to thepump segment activation signals, the segments of the sleep mode pumpcircuit 712 are selected for activation (step 818). Then, the substratebias voltage Vbb is produced by the selected segments (step 820). Theoutputs from the selected segments are combined to produce the substratebias voltage Vbb. The DRAM 100 is operated with the substrate biasvoltage Vbb (step 802). In the sleep mode, the operations of steps808-820 are repeated. If the substrate bias voltage Vbb goes lower thanthe predetermined level Vdtn (NO at step 808), pumping is ceased.

The pump signal provider 700 can be formed by the same pump signalprovider 200 of FIG. 8, as shown in FIG. 15.

In the substrate bias voltage generator 120 having the pump signalprovider as shown in FIG. 15, the sleep mode oscillator 210 is activatedby the operation mode signal 128 and the output oscillation signal 330of the sleep mode oscillator 210 is fed to the AND gate 232. Theoperations performed by the DRAM implementing the pump signal providershown in FIG. 15 are shown in FIG. 16. The operations of FIG. 16 aresimilar to those of FIG. 14. Steps 808 and 810 are reversed. In theoperations of FIG. 16, when the DRAM operation mode is determined as thesleep mode (YES at step 804), the sleep mode oscillator 210 generatesthe oscillation signal 330 (step 810) and then, it is determined whetherthe substrate bias voltage Vbb is higher than the negative determinedlevel Vdtn (step 808). Therefore, the oscillation signal is alwaysproduced in response to the operation mode signal 128, but only providedto the sleep mode pump circuit 712, when the level detection signal 220is high.

FIG. 17 shows another example of the pump signal provider 700 shown inFIG. 11. The circuit and operation of the pump signal provider shown inFIG. 17 are similar to those of FIG. 10.

In the DRAM 100 shown in FIG. 2, each of the word bootstrapping controlsignal 124 and the substrate bias control signal 126 providesindividually an indication of the refresh time for charge pumpoperation. The information on the charge pump operation can be appliedto both of the word bootstrapping voltage generator and the substratebias voltage generator of the internal voltage supply.

FIG. 18 shows another dynamic random access memory (DRAM) according toanother embodiment of the present invention. A DRAM 880 shown in FIG. 18is similar in configuration and functions to the DRAM 100 shown in FIG.2. The sleep mode pump control signal contains only a single signal 888and does not have separate component signals for a word bootstrappingvoltage generator 884 and a substrate bias voltage generator 886 of aninternal voltage supply 882.

FIG. 19 shows an example of the word bootstrapping voltage generator 884for use in the DRAM 880 of FIG. 18. The word bootstrapping voltagegenerator 884 has the same configuration and functions as the wordbootstrapping voltage generator 118 of FIG. 3 with the exception of apump segment enable controller 894. The pump segment enable controller894 has the same configuration as the pump segment enable controller 206of FIG. 3 and receives the sleep mode control signal 888 fed to theinternal voltage supply 882. The sleep mode control signal 888 includesa plurality of refresh time signal 888_1, 888_2, . . . , 888 _(—) n-1and 888_(—) n that specify the refresh time period for the DRAM 880, nbeing an integer greater than one.

The pump segment enable controller 894 outputs pump segment signals892_1, 892_2, . . . , 892 _(—) z-1 and 892 _(—) z for activatingsegments of the sleep mode pump circuit 208 in a manner similar to thepump segment enable controller of the previous embodiments. However, thepump segment signals 892_1, 892_2, . . . , 892 _(—) z-1 and 892 _(—) zare also provided to the substrate bias voltage generator 886. That is,there is only a single pump segment enable controller 894 for both theword bootstrapping voltage generator 884 and the substrate bias voltagegenerator 886.

FIG. 20 shows an example of the substrate bias voltage generator 886 foruse in the DRAM 880 of FIG. 18. The substrate bias voltage generator 886has a similar configuration and functions as the substrate bias voltagegenerator 120 of FIG. 11 but without the pump segment enable controller.The substrate bias voltage generator 886 receives pump segment signals892 from the pump segment enable controller 894 of the wordbootstrapping voltage generator 884.

While FIG. 19 illustrates the pump segment enable controller 894 as partof the word bootstrapping voltage generator 884, it will be understoodby a person of skill in the art that the pump segment enable controller894 can alternatively be part of the substrate bias voltage generator886 or be a separate component in the internal voltage supply 882.

The refresh time signal 888_1, 888_2, . . . , 888 _(—) n-1 and 888 _(—)n represent the refresh times Ref_1, Ref_2, . . . , Ref_n-1 and Ref_n,respectively, which are used for voltage boost and current pumping inboth of the word bootstrapping voltage generator 884 and the substratebias voltage generator 886. The voltage boost and current pumpingperformed by the word bootstrapping voltage generator 884 and thesubstrate bias voltage generator 886 are similar to those of the wordbootstrapping voltage generator 118 and the substrate bias voltagegenerator 120 shown in FIG. 2.

The embodiments above describe certain configurations where high and lowvalues for various signals have certain meanings. It will be understoodby one skilled in the art that these assigned meanings may be reversedand the resulting configuration changes necessary for proper functioningof the various components.

In the above described embodiments, the operation has been describedbased on positive “high” signals for the purpose of simplicity. Thecircuits may also be designed to perform the operation based on “low”active signals, in accordance with design preferences. It will beapparent to those of ordinary skill in the art that the polarity of thetransistors can be changed and the operation voltages of the differentpolarity can be provided to the transistors of the different polarity.

In the embodiments described above, the device elements and circuits areconnected to each other as shown in the figures for the sake ofsimplicity. In practical applications these devices, elements circuits,etc., may be connected directly to each other or indirectly throughother devices elements, circuits, etc. Thus, in an actual configurationof semiconductor ICs, the elements, circuits and devices are coupledeither directly or indirectly with each other.

It is apparent to one skilled in the art that numerous modifications anddepartures from the specific embodiments described herein may be madewithout departing from the spirit and scope of the invention.

The above-described embodiments of the present invention are intended tobe examples only. Alterations, modifications and variations may beeffected to the particular embodiments by those of skill in the artwithout departing from the scope of the invention, which is definedsolely by the claims appended hereto.

What is claimed is:
 1. A dynamic random access memory (DRAM) havingstorage cells, the data of which is refreshed in a sleep mode, the DRAMcomprising: a voltage producer for providing an output voltage to beused for operation of the DRAM; a voltage level detector for determiningwhether the output voltage reaches a predetermined level to provide adetermination result; and a controller for providing the control signalin response to a refresh time in the sleep mode.